This invention relates generally to semiconductor memory, and more specifically to a device and method for detecting and handling latent defects in EEPROM or flash EEPROM devices which are not readily detectable during normal read, write and erase operations of the devices.
Computers and digital systems typically use magnetic disk drives for permanent mass storage of data. However, disk drives are disadvantageous in that they are bulky and in their requirement for high precision moving mechanical parts. Consequently, they are not rugged, and are complicated and prone to reliability problems, as well as consuming significant amounts of power. Alternative form of mass storage in place of disk drives are being contemplated.
Semiconductor or solid-state memory is typically formed as an integrated circuit (IC) device with a two-dimensional array of memory cells arranged in rows and columns. Each cell contains a transistor which can be put into one of its conduction states to designate one of the memory states.
Memory devices such as Random Access Memory (RAM), Read only Memory (ROM), Programmable read-only memory (PROM), UV Erasable PROM (UVEPROM), Electrically Erasable programmable read-only memory (EEPROM) and Flash EEPROM do not suffer from these disadvantages. However, in the case of RAM, the memory is volatile, and requires constant power to maintain its memory. Consequently, RAMs are typically used as temporary working storage.
ROM, EEPROM and Flash EEPROM are all non-volatile solid state memories. They retain their memory even after power is shut down. However, ROM and PROM cannot be reprogrammed and UVPROM cannot be erased electrically.
On the other hand, EEPROM and Flash EEPROM have the further advantage of being electrically writable (or programmable) and erasable. Nevertheless, they have a limited lifetime due to the endurance-related stress the device suffers each time it goes through an erase/program cycle.
The endurance of a Flash EEPROM device is its ability to withstand a given number of program/erase cycles. The physical phenomenon limiting the endurance of conventional EEPROM and Flash EEPROM devices is trapping of electrons in the active dielectric films of the device. During programming, electrons are injected from the substrate to the floating gate through a dielectric interface. Similarly, during erasing, electrons are extracted from the floating gate to the erase gate through a dielectric interface. In both cases, some of the electrons are trapped by the dielectric interface. The trapped electrons oppose the applied electric field in subsequent program/erase cycles thereby causing the programmed threshold voltage to shift to a lower value and the erased threshold voltage to shift to a higher value. This can be seen in a gradual closure in the threshold voltage "window" between the "0" and "1" states. The window closure can become sufficiently severe to cause the reading circuitry to malfunction. If cycling is continued, the device eventually experiences catastrophic failure due to a ruptured dielectric which is known as the intrinsic breakdown of the device. Thus, with use, defects tend to build up in the memory array and typically the devices are rendered unreliable after a large number (e.g. 10.sup.4) write/erase cycles. The defects may be due to defective cells such as shorts between the various cell structures or due to defective infrastructure in the memory device such as shorts in the interconnects or device isolation.
Traditionally, EEPROM and Flash EEPROM are used in applications where semi-permanent storage of data or program is required but with a limited need for reprogramming. Defects in these devices are treated in the same manner as RAM's.
Physical defects in these devices arising from the manufacturing process are corrected at the factory similar to conventional memory devices such as RAM and magnetic disks. It is the usual practice in semiconductor memories to have redundant memory cells built into the chip. Those defective cells discovered after fabrication are discarded and remapped to these redundant cells in the array. The remapping is usually done by hard wiring at the factory. The device is then assumed to be perfect and there is little or no provision for replacing defective cells resulting from defects that appear later during normal operation. Error corrections mainly rely on schemes using error correction codes (ECC) which typically correct a limited number of random errors.
As explained above, owing to the nature of EEPROM and Flash EEPROM devices, cell failures tend to accumulate with increasing write/erase cycling. If the device is used in applications going through many write/erase cycles, the errors from the defective cells that accumulate will eventually overwhelm the ECC and render the device unreliable.
Implementations of EEPROM and Flash EEPROM as disk-like mass storage systems have been disclosed in two U.S. patent applications which have the same assignee as the present application. They are U.S. patent application, Ser. No. 337,566 of Harari et al., filed Apr. 13, 1989, now abandoned, and U.S. patent application, Ser. No. 422,949 of Gross et al., filed Oct. 17, 1989, U.S. Pat. No. 5,200,959.
In these disk-like applications, where the devices are subjected to writing and erasing a large number of times, traditional methods of handling defects in solid-state memories are inadequate because there is no effective provision for detecting and handling defects "on-the-fly" except by means of ECC.
Defect handling after the devices have left factory becomes necessary. Co-pending U.S. patent application, Ser. No. 337,566 of Harari et al. discloses a scheme of detecting and handling defects "on-the-fly" by verifying each memory operation, such as read, write or erase, after its has been performed. A verification failure indicates a defective cell, and the defective cell is remapped with a good one. Similarly co-pending U.S. patent application, Ser. No. 422,949 of Gross et al. discloses a scheme of detecting and handling defects "on-the-fly."
These defect detection schemes are based on detecting defects cell-by-cell, by sensing abnormal read, write or erase operating conditions of the memory devices. However, they are not very sensitive to weak defects which may later develop into catastrophic defects. For example, a small voltage drop caused by a weak defect may escape detection because it is still within the margin of error allowed by the read, write or erase operations.
The cell-by-cell defect detection and remapping scheme may not be the most efficient for an array of EEPROM cells. The usual memory array is accessible by a series of word lines, each connecting to all the control gates of cells row-by-row, and a series of bit lines, each connecting to all the sources or to all the drains of cells column-by-column. Failure at one cell location could affect a whole row or column of cells by virtue of connection to a common word line, erase line or bit line. Indeed, in a virtual ground architecture where the cells in a row are daisy-chained by their sources and drains, failure in one column may even propagate to neighboring columns of cells. Thus, when a cell fails to verify correctly, the failure could be caused by a defect at that cell location or by a defect from a neighboring cell location. In either case, the exact location and extent of the defect is uncertain. Without this knowledge, effective and efficient error correction can not be readily implemented.
Accordingly, it is an object of the present invention to detect weak or latent defects before they manifest as catastrophic failures during read, write or erase failures, and to determine the nature, location and extent of these defects so as to handle them efficiently.
It is another object of the invention to provide a simple and low cost EEPROM or Flash EEPROM memory system which can be reliably written and erased many times.
It is another object of the invention to provide a solid-state memory system capable of handling efficiently defects detected during use of the device.
It is another object of the invention to provide a method for efficiently handling defects detected during factory testing and field use of solid-state memory systems.